
2
Functional Block Diagram
Typical Application Schematic
LOWER
DATA
LATCHES
UPPER
DATA
LATCHES
LOWER
ENCODER
(4-BIT)
LOWER
ENCODER
(4-BIT)
UPPER
ENCODER
(4-BIT)
LOWER
COMPARATORS
WITH S/H (4-BIT)
UPPER
COMPARATORS
WITH S/H (4-BIT)
REFERENCE VOLTAGE
CLOCK GENERATOR
OE
DVSS
D0 (LSB)
D1
D2
D3
D4
D5
D6
D7 (MSB)
DVDD
CLK
11
10
9
8
7
6
5
4
3
2
1
12
LOWER
COMPARATORS
WITH S/H (4-BIT)
24
23
20
21
22
19
14
15
16
17
18
13
DVSS
VRB
VRBS
AVSS
VIN
AVDD
VRT
VRTS
AVDD
DVDD
0.6V (Typ)
2.6V (Typ)
: Ceramic Chip Capacitor 0.1
F.
: Analog GND.
:Digital GND.
NOTE: It is necessary that AVDD and DVDD pins be driven from the same supply. The gain of analog input signal can be changed by adjust-
ing the ratio of R2 to R1.
D0 (LSB)
D1
D2
D3
D4
D6
D5
CLK
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
21
22
23
24
15
14
13
D7 (MSB)
VIN
+
C9
4.7
F
HC04
CLOCK IN
+5V
C10
0.1
F
+5V
C12
0.1
F
C8
+
C7
4.7
F
C11
0.1
F
+5V
R12
+
-
CA158A
HI1175
R4
+
-
CA158A
R5
ICL8069
R11
+
-
HA2544
R2
R1
R13
R3
HI1175